A power semiconductor device is a semiconductor device used, for example, as a switch or rectifier in power electronics e.g., DC to AC inverter for motor control or DC to DC converter for switched-mode power supplies. A power semiconductor device is usually used in “commutation mode” i.e., it is either on or off, and therefore has a design optimized for such usage.
Silicon bipolar junction transistors BJT, Metal-Oxide-Semiconductor field effect transistors MOSFET and insulated gate bipolar transistors IGBT are common types of power semiconductor switching devices. Their application areas range from, without limitation, portable consumer electronics, domestic appliances, electric cars, motor control and power supplies to RF and microwave circuits and telecommunication systems.
In the last decade, Gallium Nitride (GaN) has increasingly been considered as a very promising material for use in the field of power devices with the potential to lead to increased power density, reduced on-resistance, and high frequency response. The wide band gap of the material Eg=3.39 eV results in high critical electric field Ec=3.3 MV/cm which can lead to the design of devices with a shorter drift region, and therefore lower on-state resistance, if compared to a silicon-based device with the same breakdown voltage [see U. K. Mishra et al., GaN-Based RF power devices and amplifiers, Proc. IEEE, vol 96, no 2, pp 287-305, 2008]. The use of an AlGaN/GaN heterostructure also allows the formation of a two-dimensional electron gas 2DEG at the hetero-interface where carriers can reach very high mobility μ=2000 cm2/Vs values [see U. K. Mishra et al., GaN-Based RF power devices and amplifiers, Proc. IEEE, vol 96, no 2, pp 287-305, 2008]. In addition, the piezopolarization charge present at the AlGaN/GaN heterostructure, results in a high electron density in the 2DEG layer e.g., 1×1013 cm−2. These properties can lead to the production of High Electron Mobility Transistors HEMTs and Schottky barrier diodes with very competitive performance parameters [see M. H. Kwan et al, CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications, IEDM, San Fran., December 2014, pp 17.6.1-17.6.4; S. Lenci et al., Au-free AlGaN/GaN power diode 8-in Si substrate with gated edge termination, Elec. Dev. Lett., vol 34, no 8, pp 1035, 2013]. An extensive amount of research has focused on the development of power devices using AlGaN/GaN heterostructures.
Bonding Pad over active (BPOA) area layouts, as shown in FIGS. 1, 2, 3A, 4A, and 5A, have been suggested as a design feature that can improve current density in lateral AlGaN/GaN heterostructure devices and studies which show competitive on-state and off-state characteristics for such structures can be found in literature.
By way of example, FIG. 1 shows schematically a three-dimensional perspective view of an illustrative BPOA layout with an interdigitated finger geometry. In the orientation shown in FIG. 1, the x designation shows the width, the y designation shows the height, and the z designation shows the depth. FIG. 1 is an illustrative design showing the surface of the III-V semiconductor as AlGaN 1, the source pad metal 2 of a source bonding pad SBP, a source field plate designated as FS, source/gate finger metallization 3 of the source field plate FS (also referred to as the “source metallization”), a drain pad metal 4 of a drain bonding pad DBP, a drain field plate designated as FD, drain finger metallization 5 of the drain filed plate FD (also referred to as the “drain metallization”) and the SiO2 passivation or inter-metallization dielectric 6.
Acceptable materials for the source pad metal 2 include, but are not limited to aluminum (Al). Acceptable materials for the drain pad metal 4 include, but are not limited to aluminum (Al). Acceptable materials for the source field plate FS and the source metallization 3 include, but are not limited to titanium nitride (TiN) and aluminum (Al). Acceptable materials for the drain field plate FD and the drain metallization 5 include, but are not limited to titanium nitride (TiN) and aluminum (Al).
FIG. 2 shows schematically the top view of a BPOA layout of a semiconductor device 100 with an interdigitated finger geometry. Also designated in FIG. 2 are cross-sections shown in FIGS. 3A, 4A, 5A, and 6, described further below. Each source singer metallization 3 includes the following section: the section positioned at the source pad over active area (SPOA) having a dimension designated as ss1; the section positioned at the no pad over active area (NPOA) having a dimension designated as ns1; and the section positioned at the drain pad over active area (DPOA) having a dimension designated as ds1.
Reviewing the performance of BPOA layouts, and in particular, the reliability of BPOA designs, reveals that attention should be focused on the electric field peaks observed in the inter-metallization dielectric (e.g., SiO2) when the device is biased in the off-state. Such field peaks are relevant when designing devices which are resilient to time dependent dielectric breakdown (TDDB) as high electric field in these dielectric layers can lead to increased probability of TDDB. This is especially the case where the device is exposed to high temperatures and high electric fields at the same time. TDDB depends exponentially on both temperature and the peak of the electric field. It has been observed that that the GaN based devices are meant to operate at higher junction temperatures and unlike other wide bandgap materials such as diamond or silicon carbide the thermal conductivity of GaN is lower resulting in more prominent self-heating. This is especially the case where such GaN heterostructures are grown on substrate and a thermally resistive nucleation layer such as aluminum nitride, AlN and a buffer layer are formed on top of the substrate and below the active layers to accommodate the lattice mismatch between the GaN epitaxial stack and the substrate. Such a configuration can result in additional self-heating which can make the TDDB effect even more stringent.
A distinction between different sections of a semiconductor device can be made, as seen by way of example in FIGS. 2, 3, 4, and 5. These are as follows:
FIG. 3A—No pad over active (HPOA) area;
FIG. 4A—Source pad over active (SPOA) area; and
FIG. 5A—Drain pad over active (DPOA) area.
FIGS. 3A, 4A and 5A show designated cross sections of an illustrative state of the art device as shown from the top in FIG. 2, at the noted locations and positions. Electric fields in a dielectric were simulated with off-state bias applied to the drain terminal of the device for each of these three sections, as described below.
FIGS. 3A, 4A and 5A generally show an arrangement of a state of the art BPOA semiconductor device, having a substrate 9, a buffer layer 8 above the substrate 9, a GaN layer 7 above the buffer layer 8, and a AlGaN layer 1 above the GaN layer 7. A gate terminal 10 is provided comprising a highly p-doped GaN cap 11, positioned above the AlGaN layer 1. A surface passivation dielectric 15 covers the gate 10 and is positioned between a source terminal 13 extending from a first via 12 positioned beneath the source metallization 3, and a drain terminal 14 extending from a second via 12 positioned beneath the drain metallization 5. An inter-metallization dielectric or passivation dielectric layer 6, such as an SiO2 layer, is positioned above the surface passivation dielectric 15 and between the vias 12. A gate drain offset length LGD runs from the gate 10 to the drain terminal 14, as shown by the arrow. An optional substrate terminal 16 may be provided at a lower portion of the device, but this is not a requirement.
Acceptable materials for the inter-metallization dielectric or passivation dielectric layer 6 included, but are not limited to, silicon dioxide (SiO2). Acceptable materials for the buffer layer 8 included, but are not limited to, AlN and AlGaN layers. Acceptable materials for the substrate 9 include, but are not limited to silicon (Si). Acceptable materials for the gate terminal 10 include, but are not limited to titanium nitride (TiN). Acceptable dopants for the highly p-doped GaN cap 11 include, but are not limited to, magnesium (Mg). Acceptable materials for the vias 12 include, but are not limited to tungsten (W). Acceptable materials for the source terminal 13 include, but are not limited to, titanium nitride (TiN). Acceptable materials for the drain terminal 14 include, but are not limited to, titanium nitride (TiN). Acceptable materials for the surface passivation dielectric 15 include, but are not limited to, silicon nitride (SiN). Acceptable materials for the substrate terminal 16 include, but are not limited to, silicon (Si).
FIG. 3A shows schematically the cross section taken from the area indicated in FIG. 2 in the no pad over active area (NPOA) section of a state of the art illustrative device. FIG. 3A shows a portion of the source metallization 3 having a dimension designated as ns1′ (which is a portion of ns1 shown in FIG. 2) and a portion of the drain metallization 5 having a dimension designated as nd1′ (which is a portion of nd1 shown in FIG. 2). The dimension ns1′ corresponds to an area of a portion of the source metallization 3 in the NPOA part of the semiconductor device of FIG. 2. The dimension nd1′ corresponds to an area of a portion of the drain metallization 5 in the NPOA part of the semiconductor device of FIG. 2. The specific materials shown in FIGS. 3A, 4A, and 5A, such as SiO2 and GaN, are not to be construed as limiting. Those skilled in the relevant art will appreciate materials that may be used in the arrangement of a power semiconductor device having a BPOA layout.
FIG. 4A shows schematically the cross section taken from the area indicated in FIG. 2 in the source pad over active area SPOA section of a state of the art device. FIG. 4A shows a portion of the source metallization 3 having a dimension designated as ss1′ (which is a portion of ss1 shown in FIG. 2) and a portion of the drain metallization 5 having a dimension designated as sd1′ (which is a portion of sd1 shown in FIG. 2). The dimension ss1′ corresponds to an area of a portion of the source metallization 3 in the SPOA part of the semiconductor device of FIG. 2. The dimension sd1′ corresponds to an area of a portion of the drain metallization 5 in the SPOA part of the semiconductor device of FIG. 2. FIG. 4A also shows the source pad metal 2 at the top of the device.
FIG. 5A shows schematically the cross section taken from the area indicated in FIG. 2 in the drain pad over active area DPOA section of a state of the art device. FIG. 4A shows a portion of the source metallization 3 having a dimension designated as ds1′ (which is a portion of ds1 shown in FIG. 2) and a portion of the drain metallization 5 having a dimension designated as dd1′ (which is a portion of dd1 shown in FIG. 2). The dimension ds1′ corresponds to an area of a portion of the source metallization 3 in the SPOA part of the semiconductor device of FIG. 2. The dimension dd1′ corresponds to an area of a portion of the drain metallization 5 in the SPOA part of the semiconductor device of FIG. 2. FIG. 5A also shows the drain pad metal 4 at the top of the device.
As shown in FIGS. 2, 3A, 4A and 5A, each of the source metallization fingers 3 and each of the drain metallization fingers 5 have essentially the same width along their entire lengths, regardless of whether they are in the NPOA area (corresponding to dimensions ns1 and nd1), the SPOA area (corresponding to dimensions ss1 and sd1) or the DPOA area (corresponding to dimensions ds1 and dd1). It is noted that in known configurations, such as illustrated in FIGS. 2, 3A, 4A and 5A, the following dimensional conditions apply:ns1=ss1=ds1nd1=sd1=dd1
Reviewing the designs of FIGS. 2, 3A, 4A and 5A, it becomes apparent that the distribution of the potential is significantly altered in the regions where the active area is covered by the bonding pads. This has an effect on where the electric field peaks appear in the structure. The change in the electric field peaks observed was a factor concerning mostly the dielectric layers in the device such as layer 6 in FIGS. 3A, 4A, and 5A rather than the semiconductor layers, although there is a small effect on the field distribution at the surface of the semiconductor layer as well.
The absolute electric field contour lines were plotted for the cross sections in the distinct locations (NPOA, SPOA and DPOA) of interest in the structure. The following are illustrative examples.
FIGS. 3A and 3B show respective illustrative designs and corresponding plotted electric field measurements for the electric field peaks in SiO2 at the NPOA area of the illustrated structure. In FIG. 3A, four points in the structure are labeled P1, P2, P3, and P4 indicating locations of local peaks in absolute electric field. For each of these points the magnitude of the corresponding electric field peak is shown in FIG. 3B.
FIGS. 4A and 4B show respective illustrative designs and corresponding plotted electric field measurements for the electric field peaks in SiO2 at the SPOA area of the illustrated structure. In FIG. 4A, four points in the structure are labeled P1, P2, P3, and P4 indicating locations of local peaks in absolute electric field. For each of these points the magnitude of the corresponding electric field peak is shown in FIG. 4B.
FIGS. 5A and 5B show respective illustrative designs and corresponding plotted electric field measurements for the electric field peaks in SiO2 at the DPOA area of the illustrated structure. In FIG. 5A, four points in the structure are labeled P1, P2, P3, and P4 indicating locations of local peaks in absolute electric field. For each of these points the magnitude of the corresponding electric field peak is shown in FIG. 5B.
Principal areas of concern can be identified in these plots as seen in FIGS. 3A and 3B with respect to the NPOA section, FIGS. 4B and 4B with respect to the SPOA section, and FIGS. 5A and 5B with respect to the DPOA section. The peaks that arise in the source pad (SPOA) and the drain pad (DPOA) covered regions are much higher than those observed in a region with no pad cover (NPOA). A maximum value of 7.0 MV/cm was observed in the DPOA section and a maximum value of 6.1 MV/cm was observed in the SPOA section, compared to the maximum value of 5.7 MV/cm observed in the NPOA section.
It has thus been observed that the maximum electric field peaks observed in the dielectric layers and the surface of the semiconductor can vary depending on the section of the device investigated.
Furthermore, it has been found that a high electric field may be present in the z-dimension due to the placement of the pads on the active area of the device. These locations cannot be modeled with the use of the standard 2D cross section simulation model, and therefore 3D TCAD simulations were employed to identify critical areas. FIG. 6 shows schematically a cross section along the finger metallization direction for the illustrative state of the art device of FIG. 2. One point identified as a possible concern with a BPOA structure is at the edge of the source contact pad, see P5 in FIG. 6. A similar peak can be observed at the drain contact pad edge.
BPOA layout can lead to reliability problems, among which the time dependent dielectric breakdown (TDDB) is of a significant concern especially during long term operation, high field operation and high temperature operation.
This concern arises as bonding pads over the active area change the way in which the potential is distributed in the structure when biased compared to a conventional finger structure interdigitated structure without pads over the active area. High electric fields cannot only harm the semiconductor but also the inter-metallization dielectric layers used and can lead to reliability issues such as TDDB.
To reduce the risk for TDDB, the electric field peaks in the dielectric layer must be minimized through smart field plate designs disclosed herein.
The present invention is directed to alternative structures and methods which aim at lessening the electric field peaks both within the dielectric and at the surface of the semiconductor device.
In another aspect, the electric field peaks are minimized within the dielectric layers in the third dimension (z-direction) of the semiconductor device.
The several aspects of the invention are based on re-optimizing and therefore changing the dimensions of the field plates, such as in the x or z directions, according to whether there is no pad placed directly above them, or if a low voltage source pad is placed above them, or a high voltage drain pad is placed above them.